The present invention relates to a pulse detector, in particular to a pulse detector adapted to determine whether an input clock pulse signal is in phase with a reference clock pulse signal or not and occupies a pre-defined clock pulse period.
Clock pulse signals are used, e.g., in digital telecom/datacom networks for network synchronization. Network synchronization is necessary to avoid loss of information in case digital data is transported between different nodes in the digital telecom/datacom network.
One application of pulse detection in the sense of the present invention is the phase detection in a delay compensation circuit where two redundant clock pulse signals getting out of phase due to propagation delay differences over a transmission medium are brought in phase with respect to each other before the redundancy is eliminated through selection of one of the clock pulse signals.
Another application of the present invention is the field of phase-locked loops (PLL) where the output clock pulse signal of an oscillator is compared with a reference clock signal and the resulting difference signal is used to control the oscillator frequency such that the phase of the oscillator clock pulse signal is equal to the reference clock pulse signal and maintained in this state.
Yet another application of the present invention is the handling of fault situations where the power supply either to or on printed circuit boards gets faulty. From this it follows that the clock pulse signal will not disappear immediately but gets more and more distorted. Assuming, e.g., that the clock pulse signal duty cycle initially is 50/50, it will deteriorate to 45/55, 40/60 and so forth until it finally disappears. This leads to problems since usually the clock pulse signal is not isolated until it is detected as faulty. The same applies if a circuit driver gets faulty leading to non-equally sharp rising and falling edges of the clock pulse signal and thus to a change of the duty cycle as well.
Yet another application of the present invention relates to parts of digital telecom/datacom networks that are provided in a redundant way to increase reliability. While it is not a problem if some of the clock pulse signals disappear a problem arises in case a clock pulse signal only deteriorates and is further used within the digital telecom/datacom network. Specifically, with clock pulse signals used for digital telecom/datacom network synchronization it would be extremely valuable to detect faults very early on before they affect the digital telecom/datacom system characteristics. Here, pulse detection is an effective way for early fault detection.
In particular with respect to digital telecom/datacom network synchronization, different approaches to phase detection are known in the prior art.
In EP 0 010 077 there is described a method and arrangement for regulating the phase position of a controlled clock pulse signal in relation to a reference clock pulse signal in a telecommunication network. Here, a reference clock pulse signal is delayed in a delay circuit and then compared with a controlled clock pulse signal in a first comparison circuit producing a first comparison signal in dependence on the phase difference between the delayed clock pulse signal and the controlled clock pulse signal. Also, the controlled clock pulse signal is delayed in a second delay circuit and then compared in a second comparison circuit with the reference clock pulse signal. The second comparison circuit produces a second comparison signal in dependence on the phase difference between the delayed controlled clock pulse signal and the reference clock pulse signal. The outputs of both comparison circuits are connected to a logic circuit for further control of the controlled clock pulse signal.
Another approach to phase detection is known from U.S. Pat. No. 3,947,697 and EP 0 709 966 A2 and shown in FIG. 1. Here, an input clock reference signal is supplied, firstly, via delay unit 100 to a sampling unit 102 and, secondly, directly thereto. Typically, the sampling unit 102 comprises at least two flip-flops and samples both the delayed and the non-delayed input clock reference signal for subsequent output thereof. The operation of the sampling unit 102 is triggered by a reference clock pulse signal xcfx86R(t). FIG. 2 shows the timing diagram illustrating the operation of the phase detector shown in FIG. 1. As shown in FIG. 2, at the input of the sampling unit 102 there are supplied the input clock reference signal xcfx86(t) and the delayed input clock reference signal xcfx86(txe2x88x92d). The lower part of FIG. 2 shows three typical operative conditions for the phase relationship between the input clock pulse signal xcfx86(t) and the reference clock pulse signal xcfx86R(t)). In case the reference clock pulse signal (xcfx86R(t)) is early with respect to the input clock pulse signal xcfx86(t) (xcex4 less than 0) a sample/hold operation for the input clock pulse signal xcfx86(t) and the delayed input clock pulse signal xcfx86(txe2x88x92d) leads to a sample vector [0,0]. Otherwise, in case the reference clock pulse signal xcfx86R(t) is late with respect to the input clock pulse signal xcfx86(t) and the delayed input clock pulse signal xcfx86(txe2x88x92d), the sample vector will be [1,1]. In an intermediate time period defined by the delay d of the delay unit 100, however, the simultaneous sampling of the input clock pulse signal xcfx86(t) and the delayed input clock pulse signal xcfx86(txe2x88x92d) leads to an output sample vector [1,0] thus indicating an in-phase relationship.
While the circuit illustrated in FIGS. 1 and 2 is effective to determine the phase relationship between an input clock pulse signal xcfx86(t) and a reference clock pulse signal xcfx86R(t), one problem is that the time resolution for phase detection d depends on the operation characteristics and speed of the sampling unit 102. In other words, the smaller the time resolution d for phase detection is the higher the operation speed of the sampling unit 102 must be. However, there are inherent limits to the operation speed of the sampling unit 102. In view of the ever increasing frequencies of clock pulse signals in current digital telecom/datacom networks in the GHz range and beyond the increase of the operation speed of the sampling unit 102 alone does not allow to handle the more and more demanding requirements for, e.g., phase relationship of different high frequency clock pulse signals. The same applies in case a time period of a clock pulse signal with respect to a reference clock pulse signal must be determined for pulse distortion indication.
In view of the above, a first object of the invention is to detect if a clock pulse signal is in phase with a reference clock pulse signal in an efficient manner with very high accuracy.
According to the present invention this object is achieved through a pulse detector having the features of claim 1 and through a pulse detection method having the features of claim 10.
The present invention proposes a very effective way to increase the time resolution for clock pulse signal phase detection while simultaneously reducing the hardware effort.
In particular, it is proposed to use a pulse detector having not only a single delay unit but a first delay unit and a second delay unit. The output clock pulse signal is derived between the first delay unit and the second delay unit while the input of the first delay unit and the output of the second delay unit are provided to a sampling unit operating at a sampling time defined by a reference clock pulse signal and to output the sample for phase delay indication.
Therefore, according to the present invention it is proposed to use a time window split into two parts being defined by the delay of the first delay unit and the second delay unit. The output clock pulse signal is derived at the middle of this time interval. In case an output sample vector [1,0] indicates an in-phase relationship between the input clock pulse signal and the reference clock pulse signal there is also available the information that the time delay between the output clock pulse signal and the reference clock pulse signal is at most the maximum delay of the first and/or second delay unit.
In other words, while the time resolution according to the prior art is determined by the delay of a single delay unit according to the present invention the time resolution is imp roved by a factor being determined by the greater of the two delay times of the firs t and second delay unit to the overall delay time of both delay units, typically by a factor of 2.
The increase in time resolution may be achieved by branching off the output clock pulse signal within, e.g., at the middle of the time interval being reserved to indicate phase coincidence between an input clock pulse signal and a reference clock pulse signal. Therefore, in case delay elements are built from a plurality of delay elements this advantage is achieved without any extra hardware effort at all. The present invention requires neither high frequency help signals nor PLL circuits and/or software support anyway. Since the invention uses directly the clock pulse signals to be compared the pulse detector is operated at these frequencies by simultaneously avoiding increased sampling rates being significantly higher than the frequencies of the clock pulse signals to be processed. Also, all control signals are generated within the same clock pulse system.
Therefore, the invention may be implemented using only a minimum number of simple components in hardware by achieving extremely good accuracy. Further, the pulse detector according to the present invention may be easily implemented, e.g., as ASIC circuitry.
Another object of the invention is to detect if the duty cycle of a clock pulse signal is in compliance with a reference clock period of a reference clock pulse signal or not.
According to the present invention this object is achieved through a pulse detector having the features of claim 6 and a pulse detection method having the features of claim 11.
Therefore, the same principle being applied to the detection of phase coincidence between an input clock pulse signal and a reference clock pulse signal may also be used to determine whether the duty cycle of the input clock pulse signal coincides with the duty cycle of the reference clock pulse signal. Heretofore, again a window is defined for the negative edge of the input clock pulse signal for comparison with the inverted reference clock pulse signal using the same principles outlined above and achieving related advantages.
Overall, th e pulse detector according to the present invention gives an extremely sensible and fast detector for many difficult fault situations where the signal is initially only deteriorated and does not disappear.